Semiconductor memory cell having information storage transistor and switching transistor

ABSTRACT

A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor TR 1  comprising a semiconductor channel layer Ch 1 , first and second conductive gates G 1 , G 2 , and first and second conductive layers L 1 , L 2  ; and a switching transistor TR 2  comprising a semiconductor channel forming region Ch 2 , a third conductive gate G 3 , and third and fourth conductive layers L 3 , L 4 , wherein the fourth conductive layer L 4  is connected to the second conductive gate G 2 , the first conductive gate G 1  and the third conductive gate G 3  are connected to a first memory-cell-selection line, the first conductive layer L 1  and the third conductive layer L 3  are connected to a second memory-cell-selection line, the second conductive layer L 2  is connected to a fixed potential, and the semiconductor channel forming region Ch 2  is connected to a read/write selection line.

This is a divisional of application Ser. No. 08/420,068, filed Apr. 11,1995, now U.S. Pat. No. 5,506,436, which is a divisional application ofSer. No. 08/164,812, filed Dec. 10, 1993, now U.S. Pat. No. 5,428,238.

FIELD OF THE INVENTION

The present invention relates to a semiconductor memory cell consistingof two transistors or one transistor formed by combining twotransistors.

DESCRIPTION OF THE PRIOR ART

FIG. 17 shows a conventional dynamic memory cell consisting of a singletransistor and a capacitor; the memory cell of this structure isgenerally known as a one-transistor memory cell and used as asemiconductor memory cell suitable for high density devices. In such amemory cell, the capacitance of the capacitor needs to be high enough tocause a voltage change on the associated bit line. However, the trend tosmaller plan area of the semiconductor memory cell necessitates areduction in the size of the capacitor formed in a horizontal plate-likeshape, giving rise to the problem that when reading information storedas a charge on the memory cell capacitor, the information is masked bynoise, or that, because of increasing stray capacitance on the bit linewith each generation of memory cells, only a small voltage change can becaused to the bit line. In one approach to solving this problem, thereis proposed a dynamic memory cell having a trench capacitor cellstructure (see FIG. 18) or a stacked capacitor cell structure. However,because of processing limitations on how deep the trench can be formedand how high the stack (stacked layers) can be made, there is a limit toincreasing the capacitance of the capacitor. Accordingly, it is saidthat dynamic memory cells of these structures encounter the limit ofminiaturization in the dimensional region beyond the low submicron rule.

Furthermore, with transistors forming the semiconductor memory cells,reducing the transistor's plan area beyond the low submicron rule wouldintroduce such problems as dielectric strength degradation,punch-through, etc., which would increase the possibility of leakageeven under the rated voltage condition. With conventional transistorstructures, therefore, it becomes difficult to ensure proper operationof the memory cell when the memory cell size is reduced.

To overcome the above limitations on the capacitance, there is proposeda memory cell structure wherein the memory cell is constructed with twotransistors and the transistor channel current is sensed.

In the memory cell disclosed in Japanese Patent Unexamined PublicationNo. 63-19847, for example, a capacitor C₂ coupled to the gate and drainof a MOS transistor Q₁ is connected to a word line, as shown in FIG. 3accompanying the same Patent Publication. Furthermore, the drain of thetransistor Q₁ is connected to the gate of an SOI transistor Q₂ of thecomplementary type to the transistor Q₁. The drain of the transistor Q₂is in turn connected to a fixed potential V_(D), while the source ofeach of the transistors, Q₁ and Q₂, is connected to a bit line.

In the memory cell disclosed in the above Patent Publication, since thegate electrode of the SOI (silicon-on-insulator) transistor Q₂ is formedonly on one principal surface side of the channel region thereof havingtwo principal surfaces, an extra capacitor C₂ is needed to complete thestructure of the memory cell. A further problem is that because of thecharge or electric field applied (through an insulating film) to theother principal surface of the channel region of the SOI transistor Q₂,the operation of the SOI transistor Q₂ becomes unstable and it isdifficult to reduce the channel length.

On the other hand, the memory cell disclosed in Japanese PatentUnexamined Publication No. 1-145850 is constructed with a writetransistor 18, a read transistor 19 (an SOI o transistor), and aprotective capacitor 20, as shown in FIG. 1 accompanying the same PatentPublication. The source of the write transistor 18 is connected to thegate of the read transistor 19. The cathode of the protective diode 20is connected to the drain of the read transistor 19. Further, the anodeof the protective diode 20 and the drain of the write transistor 18 areconnected to a bit line, while the source of the read transistor 19 andthe gate of the write transistor 18 are connected to a word line.

In the memory cell disclosed in the above Patent Publication, since theread transistor 19 is an SOI transistor, when the source potential iscaused to change to the same polarity as the gate potential (whenwriting a "1") the potential of the channel region changes with thechange of the gate potential, resulting in an incomplete writingcondition. It is therefore difficult to read the "1" with the expectedcertainty. Furthermore, in the read transistor 19, the gate electrode isformed only on one principal surface side of the channel region havingtwo principal surfaces. Therefore, this structure also has the problemthat because of the charge or electric field applied (through aninsulating film) to the other principal surface side of the channelregion of the read transistor 19, the operation of the read transistor19 becomes unstable and it is difficult to reduce the channel length.

The memory cells disclosed in Japanese Patent Unexamined PublicationNos. 62-141693 and 62-254462 each comprise a write transistor T1, a readtransistor T2, and a storage capacitor C, as shown in FIG. 1accompanying the former Patent Publication. The drains of thetransistors T1 and T2 are connected to a bit line, and the source of thetransistor T1 is connected to the storage capacitor and also to a firstgate of the transistor T2. Further, the gate of the transistor T1 isconnected to a write selection line, while a second gate (or a channelforming region such as a well) of the transistor T2 is connected to aread selection line.

When the read transistor T2 is formed from an SOI transistor, the firstand second gates are respectively formed on the upper and lower surfacesides of the channel region of the transistor T2 (refer to JapanesePatent Application No. 55-93521 and Japanese Patent UnexaminedPublication No. 57-18364). This structure eliminates the problem thathas placed a limitation on the reduction of the channel length. For thewrite transistor T1, on the other hand, only bulk-type transistors aredisclosed as preferred embodiments, and therefore, there is a limit tothe miniaturization of the memory cell as a whole. Furthermore, thestructure requiring each word line to be divided into a read line and awrite line has the problem of increased chip area or increased number ofstacked layers.

The present invention is concerned with the structure of a memory cellconstructed with two transistors and yet capable of solving the aboveenumerated problems. An object of the invention is to provide asemiconductor memory cell, a semiconductor memory cell for ASICs(Application Specific Integrated Circuits), and even a semiconductormemory cell with a single transistor formed by combining twotransistors, of the structure that ensures stable transistor operation,that does not require the provision of a large-capacitance capacitor asrequired in prior art DRAMs, and that allows the channel length to bereduced and achieves miniaturization of the cell.

SUMMARY OF THE INVENTION

To achieve the above object, in accordance with a first aspect of theinvention, there is provided a semiconductor memory cell, as shown inthe schematic diagram of FIG. 1, comprising:

an information storage transistor TR₁ comprising a semiconductor channellayer Ch₁ having first and second opposing principal surfaces; first andsecond conductive gates, G₁ and G₂, respectively disposed opposite thetwo principal surfaces of the semiconductor channel layer Ch₁ with firstand second barrier layer respectively interposed therebetween; and firstand second conductive regions, L₁ and L₂, respectively connected toeither end of the semiconductor channel layer Ch₁, and

a switching transistor TR₂ comprising a semiconductor channel formingregion Ch₂ having a third principal surface; a third conductive gate G₃disposed opposite the third principal surface of the semiconductorchannel forming region Ch₂ with a third barrier layer interposedtherebetween; and third and fourth conductive layers, L₂ and L₄, eachformed in a surface region of the semiconductor channel forming regionCh₂ and near either end of the third conductive gate G₃, wherein

the fourth conductive layer L₄ is connected to the second conductivegate G₂,

the first conductive gate G₁ and the third conductive gate G₃ areconnected to a first memory-cell-selection line,

the first conductive layer L₁ and the third conductive layer L₃ areconnected to a second memory-cell-selection line,

the second conductive layer L₂ is connected to a fixed potentialincluding zero potential, and

the semiconductor channel forming region Ch₂ is connected to aread/write selection line.

In the above structure, the conductive layers may be formed from alow-resistivity semiconductor, a silicide, a two-layered structure ofsilicide and semiconductor, a metal, or the like. The barrier layersserve as barriers to channel carriers, and may be formed from aninsulating material or a wide-gap semiconductor material.

In one preferred mode of the semiconductor memory cell according to thefirst aspect of the invention, as shown in the schematic diagram of FIG.4,

the information storage transistor TR₁ is formed from a transistor of afirst conductivity type,

the switching transistor TR₂ is formed from a transistor of aconductivity type opposite to the first conductivity type,

the first conductive layer L₁ is connected to the second line via afifth conductive layer L₅ which forms a rectifier junction with thefirst conductive layer L₁, and

the semiconductor channel forming region Ch₂ is connected to a secondfixed potential including zero potential.

To achieve the above object, in accordance with a second aspect of theinvention, there is provided a semiconductor memory cell, as shown inthe schematic diagram of FIG. 7, comprising:

an information storage transistor TR₁ comprising a first semiconductorchannel layer Ch₁ having first and second opposing principal surfaces;first and second conductive gates, G₁ and G₂, respectively disposedopposite the two principal surfaces of the first semiconductor channellayer Ch₁ with first and second barrier layers respectively interposedtherebetween; and first and second conductive regions, L₁ and L₂, eachconnected to either end of the first semiconductor channel layer Ch₁,and

a switching transistor TR₂ comprising a second semiconductor channellayer Ch₂ having third and fourth opposing principal surfaces; third andfourth conductive gates, G₃ and G₄, respectively-disposed opposite thetwo principal surfaces of the second semiconductor channel layer Ch₂with third and fourth barrier layers respectively interposedtherebetween; and third and fourth conductive layers, L₃ and L₄, eachconnected to either end of the second semiconductor channel region Ch₂,wherein

the fourth conductive layer L₄ is connected to the second conductivegate G₂,

the first conductive gate G₁ and the third conductive gate G₃ areconnected to a first memory-cell-selection line,

the first conductive layer L₁ and the third conductive layer L₃ areconnected to a second memory-cell-selection line,

the second conductive layer L₂ is connected to a fixed potentialincluding zero potential, and

the fourth conductive gate G₄ is connected to a read/write selectionline.

In one preferred mode of the semiconductor memory cell according to thesecond aspect of the invention, as shown in the schematic diagram ofFIG. 10,

the information storage transistor TR₁ is formed from a transistor of afirst conductivity type,

the switching transistor TR₂ is formed from a transistor of aconductivity type opposite to the first conductivity type,

the first conductive layer L₁ is connected to the second line via afifth conductive layer L₅ which forms a rectifier junction with thefirst conductive layer L₁, and

the fourth conductive gate G₄ is connected to a second fixed potentialincluding zero potential.

To achieve the above object, in accordance with a third aspect of theinvention, there is provided a semiconductor memory cell, as shown inthe schematic diagram of FIG. 12(A), comprising:

an information storage transistor TR₁ of a first conductivity type,comprising a first semiconductor channel forming region Ch₁ ; a firstconductive gate G₁ formed above the surface thereof with a first barrierlayer interposed therebetween; a first conductive region SC₁ ; and asecond conductive region SC₂, and

a switching transistor TR₂ of a second conductivity type opposite to thefirst conductivity type, comprising a second semiconductor channelforming region Ch₂ ; a second conductive gate G₂ formed above thesurface thereof with a second barrier layer interposed therebetween; athird conductive region SC₃ ; and a fourth conductive region SC₄,wherein

the first conductive gate G₁ of the information storage transistor TR₁and the second conductive gate G₂ of the switching transistor TR₂ areconnected to a first memory-cell-selection line;

the fourth conductive region SC₄ of the switching transistor TR₂ isconnected to the first semiconductor channel forming region Ch₁ of theinformation storage transistor TR₁ ;

the third conductive region SC₃ of the switching transistor TR₂ isconnected to a second memory-cell-selection line, and

the first conductive region SC₁ of the information storage transistorTR₁ is connected to a read line.

The second conductive region SC₂ of the information storage transistorTR₁ is supplied with a fixed potential including zero potential.Preferably, the first conductive region SC₁ is connected to the secondline or the third conductive region SC₃ via a rectifier junction.Preferably, the first conductive region SC₁ is formed from asemiconductor as a common region with the second semiconductor channelforming region Ch₂, the rectifier junction being formed between thecommon region and the third conductive region SC₃, and the firstsemiconductor channel forming region Ch₁ and the fourth conductiveregion SC₄ are formed from a common region. Furthermore, the secondconductive gate G₂ may be formed common with the first conductive gateG₁, as in a fifth aspect of the invention hereinafter described. In thiscase, it is desirable that the third conductive region SC₃ furtherinclude a metal layer of Mo, Al, or the like, or a silicide layer thatforms a Schottky junction with the first conductive region SC₁.

In the above structure, the conductive regions may be formed from alow-resistivity semiconductor, a silicide, a two-layered structure ofsilicide and semiconductor, a metal, or the like.

To achieve the above object, in accordance with a fourth aspect of theinvention, there is provided a semiconductor memory cell, as shown inthe schematic diagram of FIG. 14(A), comprising:

an information storage transistor TR₁ of a first conductivity type,comprising a first semiconductor channel forming region Ch₁ ; a firstconductive gate G₁ formed above the surface thereof with a first barrierlayer interposed therebetween; a first conductive region SC₁ ; and asecond conductive region SC₂, and

a switching transistor TR₂ of a second conductivity type opposite to thefirst conductivity type, comprising a second semiconductor channelforming region Ch₂ ; a second conductive gate G₂ formed above thesurface thereof with a second barrier layer interposed therebetween; athird conductive region SC₃ ; and a fourth conductive region SC₄,wherein

the first conductive gate G₁ of the information storage transistor TR₁and the second conductive gate G₂ of the switching transistor TR₂ areconnected to a first memory-cell-selection line;

the fourth conductive region SC₄ of the switching transistor TR₂ isconnected to the first semiconductor channel forming region Ch₁ of theinformation storage transistor TR₁ ;

the third conductive region SC₃ of the switching transistor TR₂ isconnected to a second memory-cell-selection line,

the second conductive region SC₂ of the information storage transistorTR₁ is connected to a fixed potential, and

the first conductive region SC₁ of the information storage transistorTR₁ is connected to the third conductive region SC₃ of the switchingtransistor TR₂, forming a rectifier junction therebetween.

A third conductive gate G₃ may be further provided opposite a thirdprincipal surface of the second semiconductor channel forming region Ch₂with a third barrier layer interposed therebetween.

To achieve the above object, in accordance with a fifth aspect of theinvention, there is provided a semiconductor memory cell, as shown inthe schematic diagram of FIG. 15(A), comprising:

a first semiconductor region SC₁ of a first conductivity type formed ina surface region of a semiconductor substrate or on an insulatingsubstrate,

a first conductive region SC₂ formed in a surface region of the firstsemiconductor region SC₁ in contacting relationship forming a rectifierjunction therebetween,

a second semiconductor region SC₃ of a second conductivity type formedin a surface region of the first semiconductor region SC₁ but spacedapart from the first conductive region SC₂,

a second conductive region SC₄ formed in a surface region of the secondsemiconductor region SC₃ in contacting relationship forming a rectifierjunction therebetween, and

a conductive gate G disposed in such a manner as to form a bridge over abarrier layer between the first semiconductor region SC₁ and the secondconductive region SC₄ and between the first conductive region SC₂ andthe second semiconductor region SC₃, wherein

the conductive gate G is connected to a first memory-cell-selectionline,

the first conductive region SC₂ is connected to a write informationselection line, and

the second conductive region SC₄ is connected to a secondmemory-cell-selection line.

To achieve the above object, in accordance with a sixth aspect of theinvention, there is provided a semiconductor memory cell, as shown inthe schematic diagram of FIG. 16(A), comprising:

a first semiconductor region SC₁ of a first conductivity type formed ina surface region of a semiconductor substrate or on an insulatingsubstrate,

a first conductive region SC₂ formed in a surface region of the firstsemiconductor region SC₁ in contacting relationship forming a rectifierjunction therebetween,

a second semiconductor region SC₃, of a second conductivity typeopposite to the first conductivity type, formed in a surface region ofthe first semiconductor region SC₁ but spaced apart from the firstconductive region SC₂,

a second conductive region SC₄ formed in a surface region of the secondsemiconductor region SC₃ in contacting relationship forming a rectifierjunction therebetween, and

a conductive gate G disposed in such a manner as to form a bridge over abarrier layer between the first semiconductor region SC₁ and the secondconductive region SC₄ and between the first conductive region SC₂ andthe second semiconductor region SC₃, wherein

the conductive gate G is connected to a first memory-cell-selectionline, and

the first semiconductor region SC₁ is connected to a secondmemory-cell-selection line.

In the semiconductor memory cell according to the fifth and sixthaspects of the invention, the first semiconductor region SC₁(corresponding to the channel forming region Ch₂), the first conductiveregion SC₂ (corresponding to a source/drain region), the secondsemiconductor region SC₃ (corresponding to a source/drain region), andthe conductive gate G constitute the switching transistor TR₂. Likewise,the second semiconductor region SC₃ (corresponding to the channelforming region Ch₁), the first semiconductor region SC₁ (correspondingto a source/drain region), the second conductive region SC₄(corresponding to a source/drain region), and the conductive gate Gconstitute the information storage transistor TR₁.

The semiconductor channel layer or semiconductor channel forming regioncan be formed from a silicon, GaAs, or the like, using a known method.Each conductive gate can be formed from a metal, an impurity-added ordoped silicon or polysilicon, a silicide, highly doped GaAs, or thelike, using a known method. Each barrier layer can be formed fromSiO_(n), Si₃ N₄, Al₂ O₃, GaAlAs, or the like, using a known method. Theconductive layers, conductive regions, or semiconductor regions can beformed from a doped silicon or polysilicon, a silicide, a highly dopedGaAs, or the like, using a known method.

In the semiconductor memory cell of the present invention, oneconductive gate of the information storage transistor and one conductivegate of the switching transistor are connected to the firstmemory-cell-selection line. The first memory-cell-selection line,therefore, need not be provided more than one, and the chip area can bereduced.

In the semiconductor memory cell of the first and second aspects of thepresent invention, the fourth conductive layer is connected to thesecond conductive gate. When writing information, the switchingtransistor conducts, and the information is stored in the form of apotential or charge on the second conductive gate of the informationstorage transistor. The threshold voltage of the information storagetransistor required at the first conductive gate, when readinginformation, varies depending on the potential or charge (information)stored on the second conductive gate. This is because the space-chargeregions overlap across the channel layer near the first and secondgates. Therefore, when reading information, the operation of theinformation storage transistor can be controlled by applying anappropriately selected potential to the first conductive gate.Information reading is accomplished by sensing the operating condition(for example, magnitude of the channel current) of the informationstorage transistor.

In the information storage transistor, a conductive gate is providedopposite each of the two principal surfaces of the semiconductor channellayer. This structure stabilizes the operation of the informationstorage transistor and facilitates short-channel transistor design. Thisalso eliminates the need for a large capacitor as required in prior artDRAMs.

The gate threshold voltage of the switching transistor is controlled bythe potential applied to the read/write selection line. When writinginformation, the switching transistor is turned on in order to store thepotential or charge on the second conductive gate, and when the writeoperation is completed, it is turned off. The stored information isretained as a potential or charge on the second conductive gate untilthe information is read out.

In the semiconductor memory cell according to the second aspect of thepresent invention, the switching transistor has the fourth conductivegate. This serves to further stabilize the operation of the switchingtransistor. This is achieved by applying to the read/write selectionline a signal for putting the switching transistor in an off conditionwithout fail during information read operation.

In the preferred modes of the semiconductor memory cell according to thefirst and second aspects of the present invention, the fifth conductivelayer is provided which forms a rectifier junction with the firstconductive layer. The provision of this fifth conductive layer serves toprevent without fail a current from flowing into the information storagetransistor during the writing of information.

In the semiconductor memory cell according to the third and fourthaspects of the present invention, the fourth conductive region of theswitching transistor is connected to the channel forming region of theinformation storage transistor. In the semiconductor memory cellaccording to the fifth aspect of the invention, the second semiconductorregion, which forms a source/drain region of the switching transistor,corresponds to the channel forming region of the information storagetransistor TR₁.

when writing information, the switching transistor conducts, and theinformation is stored as a potential or charge in the channel formingregion of the information storage transistor. The threshold voltage ofthe information storage transistor required at the first conductive gate(in the third and fourth aspects of the invention) or the conductivegate (in the fifth aspect of the invention) for read operations variesdepending on the potential or charge (information) stored in the channelforming region. Therefore, when reading information, by applying anappropriately selected potential to the first conductive gate or theconductive gate, the stored information state of the information storagetransistor can be identified by the magnitude of the channel current(including zero current). Information reading is accomplished by sensingthe operating condition of the information storage transistor.

In the semiconductor memory cell according to the sixth aspect of thepresent invention, the second semiconductor region SC₃, which forms asource/drain region of the switching transistor, corresponds to thechannel forming region Ch₁ of the information storage transistor.Further, the first semiconductor region SC₁ that corresponds to thechannel forming region of the switching transistor and also to asource/drain region of the information selection transistor is connectedto the second memory-cell-selection line.

The threshold voltage of the information storage transistor required ateach conductive gate for read operations can be varied by appropriatelyselecting the potential applied to the second memory-cell-selectionline. Therefore, the on/off conditions of the information storagetransistor and the switching transistor can be controlled byappropriately selecting the potential applied to the firstmemory-cell-selection line.

When writing information, the first line is set at a potential highenough to turn on the switching transistor, and the capacitor betweenthe regions SC₁ and SC₃ of the switching transistor is charged dependingon the potential on the second line. As a result, the information isstored in the channel forming region (the second semiconductor regionSC₃) of the information storage transistor in the form of a charge or apotential difference from the region SC₁.

When reading information, the region SC₁ is supplied with a readpotential, and the potential or charge (information) stored in thechannel forming region of the information storage transistor isconverted to a charge or a potential difference between the secondsemiconductor region SC₃, which corresponds to the channel formingregion Ch₁, and the second conductive region SC₄, which corresponds to asource/drain region. The threshold voltage of the information storagetransistor required at the conductive gate varies depending on thecharge (information). Therefore, the on/off operations of theinformation storage transistor can be controlled, when readinginformation, by applying an appropriately selected potential to theconductive gate. Information reading is accomplished by sensing theoperating condition of the information storage transistor.

In the semiconductor memory cell of the invention, the storedinformation is retained in the form of a potential, potentialdifference, or charge, but since the stored information decays with timebecause of leakage currents due to junction leaks, etc., refreshing isnecessary, and the memory cell operates in the same manner as other DRAMcells.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the principle of operation of asemiconductor memory cell according to a first aspect of the presentinvention.

FIG. 2 is a schematic cross-sectional view of a portion of asemiconductor memory cell according to Embodiment 1 of the presentinvention.

FIG. 3 is a diagram showing a modified example of Embodiment 1.

FIG. 4 is a diagram showing the principle of operation of asemiconductor memory cell according to a preferred mode of the firstaspect of the invention.

FIG. 5 is a schematic cross-sectional view of a portion of asemiconductor memory cell according to Embodiment 2 of the presentinvention.

FIG. 6 is a diagram showing a modified example of Embodiment 2.

FIG. 7 is a diagram showing the principle of operation of asemiconductor memory cell according to a second aspect of the presentinvention.

FIG. 8 is a schematic cross-sectional view of a portion of asemiconductor memory cell according to Embodiment 3 of the presentinvention.

FIG. 9 is a diagram showing a modified example of Embodiment 3.

FIG. 10 is a diagram showing the principle of operation of asemiconductor memory cell according to a preferred mode of the secondaspect of the present invention.

FIG. 11 is a schematic cross-sectional view of a portion of asemiconductor memory cell according to Embodiment 4 of the presentinvention.

FIGS. 12A to 12C shows the principle of operation of a semiconductormemory cell according to a third aspect of the present invention alongwith schematic cross-sectional views showing a portion thereof.

FIG. 13 is a schematic cross-sectional view of a portion of asemiconductor memory cell according to a modified example of the thirdaspect of the present invention.

FIGS. 14A to 14C shows the principle of operation of a semiconductormemory cell according to a fourth aspect of the present invention alongwith schematic cross-sectional views showing a portion thereof.

FIGS. 15A to 15B shows the principle of operation of a semiconductormemory cell according to a fifth aspect of the present invention alongwith a schematic cross-sectional view showing a portion thereof.

FIGS. 16A to 16C shows the principle of operation of a semiconductormemory cell according to a sixth aspect of the present invention alongwith schematic cross-sectional views showing a portion thereof.

FIG. 17 is a conceptual diagram showing a prior art one-transistormemory cell.

FIG. 18 is a cross-sectional view of a memory cell having a prior arttrench capacitor cell structure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The semiconductor memory cell of the invention will be described belowin accordance with preferred embodiments thereof.

EMBODIMENT 1

Embodiment 1 is concerned with a semiconductor memory cell according toa first aspect of the invention. The semiconductor memory cell, theprinciple of operation of which is shown in FIG. 1 and cross sections ofa portion of which are shown schematically in FIGS. 2.and 3, comprisesan information storage transistor TR₁ and a switching transistor TR₂.

The information storage transistor TR₁ comprises a semiconductor channellayer Ch₁, a first conductive gate G₁, a second conductive gate G₂, andfirst and second conductive layers, L, and L₂, each connected to eitherend of the semiconductor channel layer Ch₁. The switching transistor TR₂comprises a semiconductor channel forming region Ch₂, a third conductivegate G₃, and third and fourth conductive layers, L₃ and L₄, each formedin the surface area of the semiconductor channel forming region Ch₂ incontacting relationship forming a rectifier junction therewith. Thethird conductive gate G₃ is formed in such a manner as to bridge thethird conductive layer L₃ and the fourth conductive layer L₄.

The semiconductor channel layer Ch₁ has two opposing principal surfaces,the first principal surface MS₁ and the second principal surface MS₂.The first conductive gate G₁ is formed opposite the principal surfaceMS₁ of the semiconductor channel layer with a first barrier layer BL₁interposed therebetween. Likewise, the second conductive gate G₂ isformed opposite the principal surface MS₂ of the semiconductor channellayer with a second barrier layer BL₂ interposed therebetween. Thesemiconductor channel forming region Ch₂ has a third principal surfaceMS₃. The third conductive gate G₃ is formed opposite the third principalsurface MS₃ of the semiconductor channel forming region Ch₂ with a thirdbarrier layer BL₃ interposed therebetween.

The fourth conductive layer L₄ is connected to the second conductivegate G₂. The first conductive gate G₁ and the third conductive gate G₃are connected to a first memory-cell-selection line (for example, a wordline). In the structural example shown in FIG. 2, the first conductivegate G₁ and the third conductive gate G₃ are common. The firstconductive layer L₁ and the third conductive layer L5 are connected to asecond memory-cell-selection line (for example, a bit line). The secondconductive layer L₂ is connected to a fixed potential including zeropotential. The semiconductor channel forming region Ch₂ is connected toa read/write selection line. The read/write selection line may be acommon well or a substrate. In Embodiment 1, a common well is used. Thesecond memory-cell-selection line (for example, a bit line) need not beprovided more than one, and the chip area can be reduced.

The conductive layers may be formed from a low-resistivitysemiconductor, a silicide, a two-layered structure of silicide andsemiconductor, a metal or the like. The barrier layers serve as barriersto channel carriers, and may be formed from an insulating material or awide-gap semiconductor material.

In Embodiment 1, the information storage transistor TR₁ has an SOIstructure. That is, with the multilayered structure shown in FIG. 2, thetotal area that the information storage transistor and the switchingtransistor take up can be made approximately equal to the area that onetransistor takes up, thus allowing the chip area to be reduced.

The operation of the semiconductor memory cell will be described below,taking for example a case in which the information storage transistorTR₁ and the switching transistor TR₂ are both n-type transistors.

Potentials applied to the various lines for a memory write aredesignated as follows:

First memory-cell-selection line (e.g., word line): V_(w)

Second memory-cell-selection line (e.g., bit line) "0" write: V₀

"1" write: V₁

Read/write selection line: V_(B).sbsb.--_(W)

Potentials applied to the various lines for a memory read are designatedas follows. Note that during a read cycle, the read/write selection lineis reverse biased.

First memory-cell-selection line (e.g., word line): V_(R)

Read/write selection line: V_(B).sbsb.--_(R)

For read/write, the fixed potential to which the second conductive layerL₂ is connected is designated as follows:

Fixed potential to which the second conductive layer L₂ is connected: V₂

The threshold voltages of the information storage transistor TR₁required at the first conductive gate G₁ for memory read/writeoperations are designated as follows:

"0" read/write: V_(TH1).sbsb.--₀

"1" read/write: V_(TH1).sbsb.--₁

The potential of the second conductive gate G₂ is different between a"0" read/write and a "1" read/write. As a result, the threshold voltageof the information storage transistor TR₁ required at the firstconductive gate G₁ differs between a "0" read/write and a "1"read/write. The information storage transistor TR₁ is provided with twoconductive gates, G₁ and G₂, on opposite sides of the semiconductorchannel layer Ch₁ ; this structure serves to stabilize the operation ofthe information storage transistor TR₁, and facilitates short-channeldesign. Furthermore, a capacitor having as large capacitance as requiredin prior art DRAMs is not required.

The threshold voltage of the switching transistor TR₂ required at thethird conductive gate G₃ for a write operation is designated asV_(TH2).sbsb.--_(W). Further, the threshold voltage of the switchingtransistor TR₂ required at the third conductive gate G₃ for a readoperation is designated as V_(TH2).sbsb.--_(R). The threshold voltage ofthe switching transistor TR₂ required at the third conductive gate G₃ isdifferent between memory write and memory read because the potentialapplied to the read/write selection line differs between write and readoperations.

The relationships between the various potentials are set as follows:

    .linevert split.V.sub.W .linevert split.>.linevert split.V.sub.TH2.sbsb.--.sub.W .linevert split.

    .linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.

    .linevert split.V.sub.TH2.sbsb.--.sub.R .linevert split.>.linevert split.V.sub.R .linevert split.

The operation of the semiconductor memory cell of Embodiment 1 will bedescribed below.

Information write

When writing information "0" (second line potential: V₀) or "1" (secondline potential: V₁), the potential of the first line is V_(W).Therefore, the potential at the third conductive gate G₃ of theswitching transistor TR₂ is also V_(W). Since the potential of theread/write selection line is V_(B).sbsb.--_(W), the threshold voltage,V_(TH2).sbsb.--_(W), of the switching transistor TR₂ required at thethird conductive gate has the following relationship with respect toV_(W).

    .linevert split.V.sub.W .linevert split.>.linevert split.V.sub.TH2.sbsb.--.sub.W .linevert split.

As a result, the switching transistor TR₂ is ON. Therefore, thepotential at the second conductive gate G₂ of the information transistorTR₁ is V₀ (when writing information "0") or V₁ (when writing information"1").

When writing information, the potential at the first conductive gate G₁of the information storage transistor TR₁ is V_(W). The thresholdvoltage of the information storage transistor TR₁ required at the firstconductive gate G₁ is V_(TH1).sbsb.--₀ or V_(TH1).sbsb.--₁. If therelationship

    .linevert split.V.sub.W .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.>V.sub.TH1.sbsb.--.sub.1 .linevert split.

exists between these potentials, the information storage transistor TR₁is also ON, but writing is performed whether the information storagetransistor TR₁ is ON or OFF.

As described above, when writing information "0" or "1", the potentialat the second conductive gate G₂ of the information storage transistorTR₁ is V₀ or V₁. That is, the second conductive gate G₂ is held at apotential corresponding to the information "0" or "1", and thiscondition is substantially maintained within a prescribed time until theinformation is read out. During the information retention period afterthe information is written and before the information is read out, thevarious portions of the information storage transistor TR₁ and theswitching transistor TR₂ are set at such potentials that neithertransistor will conduct.

Information read

When reading information "0" or "1", the potential of the first line isV_(R). Therefore, the potential at the third conductive gate G₃ of theswitching transistor TR₂ is V_(R). Since the potential of the read/writeselection line is V_(B).sbsb.--_(R), a reverse bias is applied betweenthe source and the channel forming region of the switching transistorTR₂. V_(B).sbsb.--_(R) is set so that the threshold voltage,V_(TH2).sbsb.--_(R), of the switching transistor TR₂ required at thethird conductive gate has the following relationship with respect toV_(R).

    .linevert split.V.sub.TH2.sbsb.--.sub.R .linevert split.>.linevert split.V.sub.R .linevert split.

The switching transistor TR₂ is thus held OFF.

When reading information, the potential at the first conductive gate G₁of the information storage transistor TR₁ is V_(R). The thresholdvoltage of the information storage transistor TR₁ at the firstconductive gate G₁ is V_(TH1).sbsb.--₀ or V_(TH1).sbsb.--₁. Thethreshold voltage of the information storage transistor TR₁ is dependenton the potential of the second conductive gate G₂. The followingrelationship exists between these potentials.

    .linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.

Therefore, when the stored information is "0", the information storagetransistor TR₁ is OFF. On the other hand, when the stored information is"1", the information storage transistor TR₁ is ON.

Thus, the information storage transistor TR₁ is set to an ON or OFFcondition, depending on the stored information. Therefore, when thestored information is "1", current flows to the second line; when thestored information is "0", no current but the leakage current flows tothe second line. The stored information can be read in this manner bythe information storage transistor TR₁.

The above-described operating conditions of the information storagetransistor TR₁ and the switching transistor TR₂ are summarized inTable 1. The potential values given in Table 1 are only illustrativeexamples, and each potential can take any value as long as it satisfiesthe above conditions.

                  TABLE 1                                                         ______________________________________                                                     Unit: volts                                                      Memory write   "0" write        "1" write                                     ______________________________________                                        1st line potential                                                                           V.sub.W 2.0      V.sub.W                                                                             2.0                                     2nd line potential                                                                           V.sub.0 0        V.sub.1                                                                             1.0                                     Read/write line        V.sub.B-W      V.sub.B-W                               Threshold of TR.sub.2                                                                        V.sub.TH2-W                                                                           0.5      V.sub.TH2-W                                                                         0.5                                     required at 3rd gate                                                          3rd gate potential                                                                           V.sub.W 2.0      V.sub.W                                                                             2.0                                     Condition of TR.sub.2                                                                        ON               ON                                            2nd gate potential                                                                           V.sub.0 0        V.sub.1                                                                             1.0                                     Threshold of TR.sub.1                                                                        V.sub.TH1-0                                                                           1.1      V.sub.TH1-1                                                                         0.5                                     required at 1st gate                                                          1st gate potential                                                                           V.sub.W 2.0      V.sub.W                                                                             2.0                                     Condition of TR.sub.1                                                                        ON               ON                                            ______________________________________                                        Memory read    "0" read         "1" read                                      ______________________________________                                        1st line potential                                                                           V.sub.R 1.0      V.sub.R                                                                             1.0                                     Read/write line        V.sub.B-R      V.sub.B-R                               Threshold of TR.sub.2                                                                        V.sub.TH2-R                                                                           1.5      V.sub.TH2-R                                                                         1.5                                     required at 3rd gate                                                          3rd gate potential                                                                           V.sub.R 1.0      V.sub.R                                                                             1.0                                     Condition of TR.sub.2                                                                        OFF          OFF                                               2nd gate potential                                                                           V.sub.0 0        V.sub.1                                                                             1.0                                     Threshold of TR.sub.1                                                                        V.sub.TH1-0                                                                           1.1      V.sub.TH1-1                                                                         0.5                                     required at 1st gate                                                          1st gate potential     1.0            1.0                                     Condition of TR.sub.2                                                                        OFF              ON                                            Fixed potential                                                                              V.sub.2 0        V.sub.2                                                                             0                                       2nd line current                                                                             OFF              ON                                            ______________________________________                                    

A modified example of the semiconductor memory cell of Embodiment 1illustrated in FIG. 2 is shown schematically in cross section in FIG. 3.In the semiconductor memory cell shown in FIG. 2, the first conductivegate G₁ and the third conductive gate G₃ are common. By contrast, in thesemiconductor memory cell shown in FIG. 3, the second conductive gate G₂and the fourth conductive layer L₄ are common. Also, the read/writeselection line is formed from a well. While a slightly larger plan areais required as compared with the memory cell shown in FIG. 2, the memorycell shown in FIG. 3 have the advantages of relatively smooth surfacetopography, which is advantageous in lithography, and a less number ofcontacts.

EMBODIMENT 2

Embodiment 2 is concerned with a preferred mode of the semiconductormemory according to the first aspect of the invention. The semiconductormemory cell, the principle of operation of which is shown in FIG. 4 andcross sections of a portion of which are shown schematically in FIGS. 5and 6, comprises an information storage transistor TR₁ and a switchingtransistor TR₂. The structures of the information storage transistor TR₁and the switching transistor TR₂ are fundamentally the same as those ofEmbodiment 1, except for the points hereinafter described.

The information transistor TR₁ is formed from a transistor of a firstconductivity type, for example, a p-type transistor, and the switchingtransistor TR₂ is formed from a transistor of the opposite conductivitytype to that of the information storage transistor TR₁, for example, ann-type transistor. In this case, if the first conductive layer L₁ andthe second conductive layer L₂ are formed from semiconductor material,then their conductivity type should be p type. Likewise, if the firstconductive gate G₁, the second conductive gate G₂, the third conductivegate G₃, the third conductive layer L₃, and the fourth conductive layerL₄ are formed from semiconductor material, then their conductivity typeshould be n⁺ type. Alternatively, these regions may be formed from asilicide, a two-layer structure of silicide and semiconductor, or ametal. The semiconductor channel forming region Ch₂ is connected to asecond fixed potential including zero potential.

Further, the first conductive layer L₁ is connected to the second linevia a fifth conductive layer L₅ which forms a rectifier junction withthe first conductive layer. The provision of the fifth conductive layerserves to prevent without fail a current from flowing into theinformation storage transistor TR₁ during the writing of information.Furthermore, there is no possibility of the information write voltagebeing applied to the information storage transistor TR₁ and therebyinterfering with the write operation as was the case with the prior art.

The operation of the semiconductor memory cell of Embodiment 2 will bedescribed below.

The potentials of the information storage transistor TR₁ and theswitching transistor TR₂ are set to satisfy the following relationships.

    .linevert split.V.sub.W .linevert split.>.linevert split.V.sub.TH2.sbsb.--.sub.W .linevert split.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

Information write

When writing information "0" (second line potential: V₀) or "1" (secondline potential: V₁), the potential of the first line is V_(W) (>0).Therefore, the potential at the third conductive gate G₃ of theswitching transistor TR₂ is also V_(W) (>0). Since the second fixedpotential is V_(B).sbsb.--_(W), if V_(W) is set as

    .linevert split.V.sub.W .linevert split.>.linevert split.V.sub.TH2.sbsb.--.sub.W +V.sub.0 or V.sub.1 .linevert split.

where V_(TH2).sbsb.--_(W) is the threshold voltage of the switchingtransistor TR₂ required at the third conductive gate G₃, then theswitching transistor TR₂ is ON. Therefore, the potential at the secondconductive gate G₂ of the information transistor TR₁ is V₀ (when writinginformation "0") or V₁ (when writing information "1").

when writing information, the potential at the first conductive gate G₁of the information storage transistor TR₁ is V_(W) (>0). Therefore, whenV₀ or V₁ <V_(W) -V_(TH1).sbsb.--₁, the information storage transistorTR₁ is OFF. Even if it is ON, current flow is blocked by the presence ofthe rectifier junction between the first conductive layer L₁ and thefifth conductive layer L₅.

As described above, when writing information "0" or "1", the potentialat the second conductive gate G₂ of the information storage transistorTR₁ is V₀ or V₁. That is, the second conductive gate G₂ is held at apotential corresponding to the information "0" or "1", and thiscondition is substantially maintained until the information is read out.During the information retention period after the information is writtenand before the information is read out, the various portions of theinformation storage transistor TR₁ and the switching transistor TR₂ areset at such potentials that neither transistor will conduct.

Information read

When reading information "0" or "1", the potential of the first line isV_(R) (<0). Therefore, the potential at the third conductive gate G₃ ofthe switching transistor TR₂ is V_(R) (<0), and the switching transistorTR₂ remains OFF unless the potential of the second line is made morenegative than V_(R) -V_(TH2).sbsb.--_(R). Normally, for a readoperation, the second line is set at a small potential and informationis read by sensing the current.

The potential at the first conductive gate G₁ of the information storagetransistor TR₁ is V_(R) (<0). The threshold voltage of the informationstorage transistor TR₁ required at the first conductive gate G₁ isV_(TH1).sbsb.--₀ or V_(TH1).sbsb.--₁. The threshold voltage of theinformation storage transistor TR₁ is dependent on the potential of thesecond conductive gate G₂. The following relationship exists betweenthese potentials.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

Therefore, when the stored information is "0", the information storagetransistor TR₁ is ON. On the other hand, when the stored information is"1", the information storage transistor TR₁ is OFF.

Thus, the information storage transistor TR₁ is set to an ON or OFFcondition, depending on the stored information. The second conductivelayer L₂ of the information storage transistor TR₁ is connected to thefixed potential (V₂); therefore, when the stored information is "0",current flows to the second line, and when the stored information is"1", current does not flow to the second line. The stored informationcan be read in this manner by the information storage transistor TR₁.

A cross section of a portion of the semiconductor memory cell ofEmbodiment 2 is shown schematically in FIG. 5. The semiconductor memorycell of Embodiment 2 is fundamentally the same as the semiconductormemory cell shown in FIG. 2, except that the information storagetransistor TR₁ and the switching transistor TR₂ are of differentconductivity types and that the first conductive layer L₁ is connectedto the second line via the n-type fifth conductive layer L₅ which formsa rectifier junction with the p-type first conductive layer L₁.

Table 2 summarizes the operating conditions of the semiconductor memorycell in which the information storage transistor TR₁ is formed from ap-type transistor and the switching transistor TR₂ is formed from ann-type transistor.

                  TABLE 2                                                         ______________________________________                                                     Unit: volts                                                      Memory write   "0" write        "1" write                                     ______________________________________                                        1st line potential                                                                           V.sub.W 1.5      V.sub.W                                                                             1.5                                     2nd line potential                                                                           V.sub.0 0        V.sub.1                                                                             1.0                                     Read/write line        V.sub.B-W      V.sub.B-W                               Threshold of TR.sub.2                                                                        V.sub.TH2-W                                                                           0.5      V.sub.TH2-W                                                                         0.5                                     required at 3rd gate                                                          3rd gate potential                                                                           V.sub.W 1.5      V.sub.W                                                                             1.5                                     Condition of TR.sub.2                                                                        ON               ON                                            2nd gate potential                                                                           V.sub.0 0        V.sub.1                                                                             1.0                                     1st gate potential                                                                           V.sub.W 1.5      V.sub.W                                                                             1.5                                     Condition of TR.sub.1                                                                        OFF              OFF                                           ______________________________________                                        Memory read    "0" read         "1" read                                      ______________________________________                                        1st line potential                                                                           V.sub.R -1.0     V.sub.R                                                                             -1.0                                    3rd gate potential                                                                           V.sub.R -1.0     V.sub.R                                                                             -1.0                                    Condition of TR.sub.2                                                                        OFF              OFF                                           2nd gate potential                                                                           V.sub.0 0        V.sub.1                                                                             1.0                                     Threshold of TR.sub.1                                                                        V.sub.TH1-0                                                                           -0.5     V.sub.TH1-1                                                                         -1.1                                    required at 1st gate                                                          1st gate potential     -1.0           -1.0                                    Condition of TR.sub.1                                                                        ON               OFF                                           Fixed potential        V.sub.2        V.sub.2                                 2nd gate current                                                                             ON               OFF                                           ______________________________________                                    

The potential values given in Table 2 are only illustrative examples,and each potential can take any value as long as it satisfies the aboveconditions.

A modified example of the semiconductor memory cell illustrated in FIG.5 is shown schematically in cross section in FIG. 6. The semiconductormemory cell shown is fundamentally the same as the semiconductor memorycell shown in FIG. 3, except that the information storage transistor TR₁and the switching transistor TR₂ are of different conductivity types andthat the first conductive layer L₁ is connected to the second line viathe n-type fifth conductive layer L₅ which forms a rectifier junctionwith the p-type first conductive layer L₁.

Embodiment 3

Embodiment 3 is concerned with a semiconductor memory cell according toa second aspect of the invention. The semiconductor memory cell, theprinciple of operation of which is shown in FIG. 7 and cross sections ofa portion of which are shown schematically in FIGS. 8 and 9, comprisesan information storage transistor TR₁ and a switching transistor TR₂.The information storage transistor TR₁ comprises a first semiconductorchannel layer Ch₁, a first conductive gate G₁, a second conductive gateG₂, and first and second conductive layers, L₁ and L₂, each connected toeither end of the first semiconductor channel layer Ch₁. The switchingtransistor TR₂ comprises a second semiconductor channel layer Ch₂, athird conductive gate G₃, a fourth conductive gate G₄, and third andfourth conductive layers, L₃ and L₄, each connected to either end of thesecond semiconductor channel layer Ch₂. In Embodiment 3, the informationstorage transistor TR₁ and the switching transistor TR₂ both have an SOIstructure (including a structure in which the barrier layer is formedfrom a wide-gap semiconductor, for example, GaAlAs as compared withGaAs).

The first semiconductor channel layer Ch₁ has two opposing principalsurfaces, the first principal surface MS₁ and the second principalsurface MS₂. The first conductive gate G₁ is formed opposite theprincipal surface MS₁ of the first semiconductor channel layer with afirst barrier layer BL₁ interposed therebetween. Likewise, the secondconductive gate G₂ is formed opposite the principal surface MS₂ of thefirst semiconductor channel layer with a second barrier layer BL₂interposed therebetween.

The second semiconductor channel layer Ch₂ has two opposing principalsurfaces, the third principal surface MS₃ and the fourth principalsurface MS₄. The third conductive gate G₃ is formed opposite the thirdprincipal surface MS₃ of the second semiconductor channel layer Ch₂ witha third barrier layer BL₃ interposed therebetween. Likewise, the fourthconductive gate G₄ is formed opposite the fourth principal surface MS₄of the second semiconductor channel layer Ch₂ with a third barrier layerBL₄ interposed therebetween.

The fourth conductive layer L₄ is connected to the second conductivegate G₂. In Embodiment 3, the fourth conductive layer L₄ and the secondconductive gate G₂ are common. The first conductive gate G₁ and thethird conductive gate G₃ are connected to a first memory-cell-selectionline (for example, a word line). The first conductive layer L₁ and thethird conductive layer L₃ are connected to a secondmemory-cell-selection line (for example, a bit line). The secondconductive layer L₂ is connected to a fixed potential including zeropotential. The fourth conductive gate G₄ is connected to a read/writeselection line.

The semiconductor memory cell of Embodiment 3 is different from thesemiconductor memory cell of Embodiment 1 in that the switchingtransistor TR₂ has the fourth conductive gate G₄. This serves to furtherstabilize the operation of the switching transistor TR₂ and yet allowsfurther miniaturization.

When the information storage transistor TR₁ and the switching transistorTR₂ are both n-type transistors, the operation of the semiconductormemory cell is the same as that described in Embodiment 1 (see Table 1),and therefore, detailed explanation thereof is not repeated here.

A modified example of the semiconductor memory cell of Embodiment 3illustrated in FIG. 8 is shown schematically in cross section in FIG. 9.In the semiconductor memory cell shown in FIG. 8, the second conductivegate G₂ and the fourth conductive layer L₄ are common. By contrast, inthe semiconductor memory cell shown in FIG. 9, the first conductive gateG₁ and the third conductive gate G₃ are formed in the same substratesurface. The first conductive gate G₁ and the third conductive gate G₃may be connected to each other. While a slightly larger plan area isrequired than that of the memory cell shown in FIG. 8, the memory cellshown in FIG. 9 has the advantage that the first semiconductor channellayer Ch₁ and the second semiconductor channel layer Ch₂ can be formedusing a single high-quality semiconductor layer whereas two such layersare needed in the structure of the semiconductor memory cell shown inFIG. 8. There is a further advantage that the first conductive gate G₁and the third conductive gate G₃ can be made common.

Embodiment 4

Embodiment 4 is concerned with a preferred mode of the semiconductormemory cell according to the second aspect of the invention. Thesemiconductor memory cell, the principle of operation of which is shownin FIG. 10 and a cross section of a portion of which is shownschematically in FIG. 11, comprises an information storage transistorTR₁ and a switching transistor TR₂. The structures of the informationstorage transistor TR₁ and the switching transistor TR₂ arefundamentally the same as those of Embodiment 3, except for the pointshereinafter described.

The information transistor TR₁ is formed from a transistor of a firstconductivity type, for example, a p-type transistor, and the switchingtransistor TR₂ is formed from a transistor of the opposite conductivitytype to that of the information storage transistor TR₁, for example, ann-type transistor. In this case, if the first conductive layer L₁ andthe second conductive layer L₂ are formed from semiconductor material,then their conductivity type should be p type. Likewise, if the firstconductive gate G₁, the second conductive gate G₂, the third conductivegate G₃, the fourth conductive gate G₄, the third conductive layer L₃,and the fourth conductive layer L₄ are formed from semiconductormaterial, then their conductivity type should be n⁺ type. The fourthconductive gate G₄ is connected to a second fixed potential includingzero potential.

Further, the first conductive layer L₁ is connected to the second linevia an n-type fifth conductive layer L₅ which forms a rectifier junctionwith the p-type first conductive layer L₁.

A cross section of a portion of the semiconductor memory cell ofEmbodiment 4 is shown schematically in FIG. 11. The semiconductor memorycell of Embodiment 3 is fundamentally the same as the semiconductormemory cell shown in FIG. 9, except that the first and second conductivelayers, L₁ and L₂, are of different conductivity type and that the firstconductive layer L₁ is connected to the second line via the n⁺ fifthconductive layer L₅ which forms a rectifier junction with the p-typefirst conductive layer L₁. In FIG. 11, the fifth conductive layer L₅ andthe rectifier junction between the first conductive layer L₁ and thefifth conductive layer L₅ are shown in schematic form for simplicity. Itwill also be appreciated that the first conductive gate G₁ and the thirdconductive gate G₃ may be connected to each other.

When the information storage transistor TR₁ is formed from a p-typetransistor and the switching transistor TR₂ from an n-type transistor,the operation of the semiconductor memory cell is the same as thatdescribed in Embodiment 2 (see Table 2), and therefore, detailedexplanation thereof is not repeated here.

Embodiment 5

Embodiment 5 is concerned with a semiconductor memory cell according toa third aspect of the invention. The semiconductor memory cell, theprinciple of operation of which is shown in FIG. 12(A) and a crosssection of a portion of which is shown schematically in FIG. 12(B),comprises an information storage transistor TR₁ formed from afield-effect transistor of a first conductivity type (for example, ntype) and a switching transistor TR₂ formed from a field-effecttransistor of a second conductivity type (for example, p type).

The information storage transistor TR₁ comprises a first channel formingregion Ch₁ of the second conductivity type, a first conductive gate G₁formed above the first semiconductor channel forming region Ch₁ with afirst barrier layer interposed therebetween, and first and secondconductive regions, SC₁ and SC₂, separated by the first conductive gateG₁. The first conductive gate G₁ is formed in such a manner as to bridgethe first conductive region SC₁ and the second conductive region SC₂.

The switching transistor TR₂ comprises a second semiconductor channelforming region Ch₂ of the first conductivity type, a second conductivegate G₂ formed above the second semiconductor channel forming region Ch₂with a second barrier layer interposed therebetween, a third conductiveregion SC₃, and a fourth conductive region SC₄. The second conductivegate G₂ is formed in such a manner as to bridge the third conductiveregion SC₃ and the fourth conductive region SC₄.

More specifically, the conductive regions are the source and drainregions. The first and second conductive regions, SC₁ and SC₂, are eachformed from a low-resistivity semiconductor of the opposite conductivitytype to that of the first semiconductor channel forming region Ch₁, orfrom a metal or a silicide that forms a rectifier junction with thefirst semiconductor channel forming region Ch₁. Likewise, the third andfourth conductive regions, SC₃ and SC₄, are each formed from alow-resistivity semiconductor of the opposite conductivity type to thatof the second semiconductor channel forming region Ch₂, or from a metalor a silicide that forms a rectifier junction with the secondsemiconductor channel forming region Ch₂.

The first conductive gate G₁ of the storage transistor TR₁ and thesecond conductive gate G₂ of the switching transistor TR₂ are connectedto a first memory-cell-selection line (for example, a word line). Thefourth conductive region SC₄ of the switching transistor TR₂ isconnected to, or formed common with, the channel forming region Ch₁ ofthe storage transistor TR₁. The third conductive region SC₃ of theswitching transistor TR₂ is connected to a second memory-cell-selectionline (for example, a bit line. The first conductive region SC₁ of theinformation storage transistor TR₁ is connected to a read line. Thesecond conductive region SC₂ is connected to a fixed potential includingzero potential.

Potentials applied to the various lines for a memory write aredesignated as follows:

First memory-cell-selection line (e.g., word line): V_(w)

Second memory-cell-selection line (e.g., bit line)

"0" write: V₀

"1" write: V₁

Read potential is designated as follows:

First memory-cell-selection line (e.g., word line): V_(R)

Also, for a memory read, the potential of the read line to which thefirst conductive region SC₁ of the information storage transistor TR₁ isconnected is designated as follows:

Read line potential: V₂

The threshold voltages of the information storage transistor TR₁required at the first conductive gate G₁ for read operations aredesignated as follows:

"0" read: V_(TH1).sbsb.--₀

"1" read: V_(TH1).sbsb.--₁ The potential of the channel forming regionCh₁ is different between a "0" read and a "1" read. As a result, thethreshold voltage of the information storage transistor TR₁ required atthe first conductive gate G₁ differs between a "0" read and a "1" read.However, the structure does not require the provision of a largecapacitor as required in the prior art DRAM shown in FIG. 17.

The potential of the information storage transistor TR₁ is set tosatisfy the following relationship.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

The operation of the semiconductor memory cell of Embodiment 5 will bedescribed below.

Information write

When writing information "0" (second line potential: V₀) or "1" (secondline potential: V₁), the potential of the first line is set at V_(W)(<0). As a result, the potential at the second conductive gate G₂ of theswitching transistor TR₂ is also V_(W) (<0). Therefore, the switchingtransistor TR₂ is ON. Consequently, the potential of the channel formingregion Ch₁ of the information storage transistor TR₁ is V₀ (when writinginformation "0") or V₁ (when writing information "1". Or V_(W) -V_(TH2)when .linevert split.V_(W) .linevert split.<.linevert split.V₁ +v_(TH2).linevert split.).

When writing information, the potential at the first conductive gate G₁of the information storage transistor TR₁ is V_(W) (<0). Therefore, theinformation storage transistor TR₁ is OFF. Thus, when writinginformation "0" or "1", the potential of the channel forming region Ch₁of the information storage transistor TR₁ is V₀ (when writinginformation "0") or V₁ or V_(W) -V_(TH2) (when writing information "1").This condition changes with time because of leakage currents (betweenthe substrate and the semiconductor channel forming region Ch₁ of theinformation storage transistor TR₁, off currents of the switchingtransistor TR₂, etc.), but is maintained within an allowable range untilthe information is read out. More specifically, during the informationretention period after the information is written and before theinformation is read out, the various portions of the information storagetransistor TR₁ and the switching transistor TR₂ are set at suchpotentials that neither transistor will conduct. Furthermore, theso-call refresh operation is performed before the change in thepotential of the channel forming region Ch₁ of the information storagetransistor TR₁ becomes large enough to cause errors in read operations.

Information read

When reading information "0" or "1", the potential of the first line isV_(R) (>0). As a result, the potential at the second conductive gate G₂of the switching transistor TR₂ is V_(R) (>0), and the switchingtransistor TR₂ is OFF.

The potential at the first conductive gate G₁ of the information storagetransistor TR₁ is V_(R) (>0). Also, the threshold voltage of theinformation storage transistor TR₁ required at the first conductive gateG₁ is V_(TH1).sbsb.--₀ or V_(TH1).sbsb.--₁. The threshold voltage of theinformation storage transistor TR₁ is dependent on the potential of thechannel forming region Ch₁. The following relationship exists betweenthese threshold voltages.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

Therefore, when the stored information is "0", the information storagetransistor TR₁ is ON. On the other hand, when the stored information is"1", the information storage transistor TR₁ is OFF.

Thus, the information storage transistor TR₁ is set to an ON or OFFcondition, depending on the stored information. Since the firstconductive region SC₁ of the information storage transistor TR₁ isconnected to the read line or the second line, current flows or does notflow to the information storage transistor TR₁, depending on the storedinformation ("0" or "1"). The stored information can be read out in thismanner by the information storage transistor TR₁. A mode in which thefirst conductive region SC₁ of the information storage transistor TR₁ isconnected to the second line will be described hereinafter.

The above-described operating conditions of the information storagetransistor TR₁ and the switching transistor TR₂ are summarized in Table3. The potential values given in Table 3 are only illustrative examples,and each potential can take any value as long as it satisfies the aboveconditions.

                  TABLE 3                                                         ______________________________________                                                     Unit: volts                                                      Memory write   "0" write        "1" write                                     ______________________________________                                        1st line potential                                                                           V.sub.W -3.0     V.sub.W                                                                             -3.0                                    2nd line potential                                                                           V.sub.0 0        V.sub.1                                                                             -2.0                                    2nd gate potential                                                                           V.sub.W -3.0     V.sub.W                                                                             -3.0                                    Condition of TR.sub.2                                                                        ON               ON                                            Potential of channel                                                                         V.sub.0 0        V.sub.1                                                                             -2.0                                    forming region                                                                1st gate potential                                                                           V.sub.W -3.0     V.sub.W                                                                             -3.0                                    Condition of TR.sub.1                                                                        OFF              OFF                                           ______________________________________                                        Memory read    "0" read         "1" read                                      ______________________________________                                        1st line potential                                                                           V.sub.R 1.0      V.sub.R                                                                             1.0                                     2nd gate potential                                                                           V.sub.R 1.0      V.sub.R                                                                             1.0                                     Condition of TR.sub.2                                                                        OFF              OFF                                           Potential of channel                                                                         V.sub.0 0        V.sub.1                                                                             -2.0                                    forming region                                                                Threshold of TR.sub.1                                                                        V.sub.TH1-0                                                                           0.5      V.sub.TH1-1                                                                         1.1                                     required at 1st gate                                                          1st gate potential     1.0            1.0                                     Condition of TR.sub.1                                                                        ON               OFF                                           Read line potential                                                                          0.5 V*           0.5 V*                                        ______________________________________                                         *2nd line potential: 1 V for FIG. 12(c)                                  

In Embodiment 5, it is possible to omit the read line. Morespecifically, the read line may be formed common with the second line.In this case, the first conductive region SC₁ is connected to the secondline via a p-n junction or a Schottky junction type rectifying diode D₂,as indicated by a dotted line in FIG. 12(B). This semiconductor memorycell structure can be realized, for example, in the structure shown inFIG. 12(C). In the structure shown in FIG. 12(C), the diode D₂ is formedby forming the first conductive region SC₁ from a semiconductor andforming the third conductive region SC₃ in the surface area thereof, theconductivity type of the third conductive region SC₃ being opposite tothat of the first conductive region SC₁. Furthermore, in thesemiconductor memory cell shown in FIG. 12(C), the first semiconductorchannel forming region Ch₁ and the fourth conductive region SC₄ areformed of a common region. Likewise, the first conductive region SC₁ andthe second semiconductor channel forming region Ch₂ are formed of acommon region.

In the thus structured semiconductor memory cell, the readout voltageapplied to the second line must be small enough that a large forwardcurrent will not flow across the junction between the first conductiveregion SC₁ and the third. conductive region SC₃ (0.4 V or less in thecase of a p-n junction); otherwise, latch-up may occur. One way toprevent the latch-up condition is to form the third conductive regionSC₃ from a silicide or a metal so that the third conductive region SC₃and the first conductive region SC₁ form a junction such as a Schottkyjunction where majority carriers essentially form the forward current.

As a structure that can utilize the conventional MOS technology, thethird conductive region SC₃ may be formed, as shown in FIG. 13, forexample, from a p-type semiconductor region SC_(3P) and a metal layer ofMo, Al, etc. or a silicide layer, SC_(3S), that can form a Schottkyjunction with the first conductive region SC₁. In the semiconductormemory cell shown in FIG. 13, the first conductive gate G₁ and thesecond conductive gate G₂ are formed common. Also, the reference sign Edesignates an electrode Al or Al/TiN/Ti triple layer formed on the thirdconductive region SC₃, and the first conductive region SC₁ is formed,for example, from an n-type semiconductor.

Thus, this embodiment provides the structure that can also be employedin CMOS fabrication, and therefore, the structure, among others, thestructure shown in FIG. 12(B), is particularly suitable for DRAMsintegrated in CMOS ASICs.

Embodiment 6

Embodiment 6 is concerned with a semiconductor memory cell according toa fourth aspect of the invention. The semiconductor memory cell ofEmbodiment 6, the principle of operation of which is shown in FIG. 14(A)and a cross section of a portion of which is shown schematically in FIG.13(B), comprises an information storage transistor TR₁ of a firstconductivity type (for example, n type) and a switching transistor TR₂of a second conductivity type (for example, p type) opposite to thefirst conductivity type.

The information storage transistor TR₁ comprises a first conductive gateG₁, first and second conductive regions, SC₁ and SC₂, formed, forexample, from an n⁺ semiconductor, and a first semiconductor channelforming region Ch₁ (common with a p-well in the example shown in FIG.14(B)). The first conductive region SC₁ and the second conductive regionSC₂ each form a rectifier junction with the surface area of the firstsemiconductor channel forming region Ch₁. The first conductive gate G₁is formed opposite a first principal surface of the first semiconductorchannel forming region Ch₁, with a first barrier layer interposedtherebetween, in such a manner as to bridge the first and secondconductive regions SC₁ and SC₂.

The switching transistor TR₂ comprises a second conductive gate G₂,third and fourth conductive regions, SC₃ and SC₄, formed, for example,from a p⁺ semiconductor, and a second semiconductor channel formingregion Ch₂. The third conductive region SC₃ and the fourth conductiveregion SC₄ are connected to the second semiconductor channel formingregion Ch₂. The second conductive gate G₂ is formed opposite a secondprincipal surface of the second semiconductor channel forming region Ch₂with a second barrier layer interposed therebetween.

The first conductive gate G₁ of the information storage transistor TR₁and the second conductive gate G₂ of the switching transistor TR₂ areconnected to a first memory-cell-selection line (for example, a wordline). The fourth conductive region SC₄ of the switching transistor TR₂is connected to the channel forming region Ch₁ of the informationstorage transistor TR₁. The third conductive region SC₃ of the switchingtransistor TR₂ is connected to a second memory-cell-selection line (forexample, a bit line). The second conductive region SC₂ of theinformation storage transistor TR₁ is connected to a fixed potential.The first conductive region SC₁ of the information storage transistorTR₁ is connected to the third conductive region SC₃ of the switchingtransistor TR₂, forming at their boundary a rectifier junction of p-njunction or Schottky junction type. With the impurity concentration inthe first conductive region SC₁ at the junction adjusted to 2×10¹⁹ cm⁻³or less, the dielectric strength or leakage current characteristic atthe rectifier junction can be improved.

Potentials applied to the various lines for a memory write aredesignated as follows:

First memory-cell-selection line (e.g., word line): V_(W)

Second memory-cell-selection line (e.g., bit line)

"0" write: V₀

"1" write: V₁

Read potential is designated as follows:

First memory-cell-selection line (e.g., word line): V_(R)

Also, for a memory read, the fixed potential to which the secondconductive region SC₂ of the information storage transistor TR₁ isconnected is designated as follows:

Fixed potential: V₂

The threshold voltages of the information storage transistor TR₁required at the first conductive gate G₁ for read operations aredesignated as follows:

"0" read: V_(TH1).sbsb.--₀

"1" read: V_(TH1).sbsb.--₁

The potential of the channel forming region Ch₁ is different between a"0" read and a "1" read. As a result, the threshold voltage of theinformation storage transistor TR₁ required at the first conductive gateG₁ differs between a "0" read and a "1" read. However, the structuredoes not require the provision of a large capacitor as required in theprior art DRAM.

The potential of the information storage transistor TR₁ is set tosatisfy the following relationship.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

The operation of the semiconductor memory cell of Embodiment 6 will bedescribed below.

Information write

When writing information "0" (second line potential: V₀) or "1" (secondline potential: V₁), the potential of the first line is set at V_(W)(<0). As a result, the potential at the second conductive gate G₂ of theswitching transistor TR₂ is also V_(W) (<0). Therefore, the switchingtransistor TR₂ is ON. Consequently, the potential of the channel formingregion Ch₁ of the information storage transistor TR₁ is V₀ (when writinginformation "0") or V₁ (when writing information "1". Or V_(W) -V_(TH2)when .linevert split.V_(W) .linevert split.<.linevert split.V₁ +V_(TH2).linevert split.).

When writing information, the potential at the first conductive gate G₁of the information storage transistor TR₁ is V_(W) (<0). Therefore, theinformation storage transistor TR₁ is OFF. Thus, when writinginformation "0" or "1", the potential of the channel forming region Ch₁of the information storage transistor TR₁ is V₀ (when writinginformation "0") or V₁ or V_(W) -V_(TH2) (when writing information "1").This condition changes with time because of leakage currents (betweenthe substrate and the semiconductor channel forming region Ch₁ of theinformation storage transistor TR₁, off currents of the switchingtransistor TR₂, etc.), but is maintained within an allowable range untilthe information is read out. More specifically, during the informationretention period after the information is written and before theinformation is read out, the various portions of the information storagetransistor TR₁ and the switching transistor TR₂ are set at suchpotentials that neither transistor will conduct. Furthermore, theso-call refresh operation is performed before the change in thepotential of the channel forming region Ch₁ of the information storagetransistor TR₁ becomes large enough to cause errors in read operations.

The first conductive region SC₁ of the information storage transistorTR₁ is connected to the third conductive region SC₃ of the switchingtransistor TR₂, forming at their boundary a rectifier junction of p-njunction or Schottky junction type. This perfectly prevents the currentflow to the first conductive region SC₁ during the writing ofinformation.

Information read

When reading information "0" or "1", the potential of the first line isV_(R) (>0). As a result, the potential at the second conductive gate G₂of the switching transistor TR₂ is V_(R) (>0), and the switchingtransistor TR₂ is OFF.

The potential at the first conductive gate G₁ of the information storagetransistor TR₁ is V_(R) (>0). Also, the threshold voltage of theinformation storage transistor TR₁ required at the first conductive gateG₁ is V_(TH1).sbsb.--₀ or V_(TH1).sbsb.--₁. The threshold voltage of theinformation storage transistor TR₁ is dependent on the potential of thechannel forming region Ch₁. The following relationship exists betweenthese threshold voltages.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

Therefore, when the stored information is "0", the information storagetransistor TR₁ is ON. On the other hand, when the stored information is"1", the information storage transistor TR₁ is OFF.

Thus, the information storage transistor TR₁ is set to an ON or OFFcondition, depending on the stored information. Since the secondconductive region SC₂ of the information storage transistor TR₁ isconnected to the fixed potential, current flows or does not flow to theinformation storage transistor TR₁, depending on the stored information("0" or "1"). The stored information can be read out in this manner bythe information storage transistor TR₁. The above-described operatingconditions of the information storage transistor TR₁ and the switchingtransistor TR₂ are summarized in Table 4. The potential values given inTable 4 are only illustrative examples, and each potential can take anyvalue as long as it satisfies the above conditions.

                  TABLE 4                                                         ______________________________________                                                     Unit: volts                                                      Memory write   "0" write        "1" write                                     ______________________________________                                        1st line potential                                                                           V.sub.W -2.5     V.sub.W                                                                             -2.5                                    2nd line potential                                                                           V.sub.0 0        V.sub.1                                                                             -2.0                                    2nd gate potential                                                                           V.sub.W -2.5     V.sub.W                                                                             -2.5                                    Condition of TR.sub.2                                                                        ON               ON                                            Potential of TR.sub.1                                                                        V.sub.0 0        V.sub.1                                                                             -1.0                                    channel forming                                                               region                                                                        1st gate potential                                                                           V.sub.W -2.5     V.sub.W                                                                             -2.5                                    Condition of TR.sub.1                                                                        OFF              OFF                                           ______________________________________                                        Memory read    "0" read         "1" read                                      ______________________________________                                        1st line potential                                                                           V.sub.R 0.9      V.sub.R                                                                             0.9                                     2nd gate potential                                                                           V.sub.R 0.9      V.sub.R                                                                             0.9                                     Condition of TR.sub.2                                                                        OFF              OFF                                           Potential of TR.sub.1                                                                        V.sub.0 0        V.sub.1                                                                             -2.0                                    channel forming                                                               region                                                                        Threshold of TR.sub.1                                                                        V.sub.TH1-0                                                                           0.5      V.sub.TH1-1                                                                         1.1                                     required at 1st gate                                                          1st gate potential     0.9            0.9                                     Condition of TR.sub.1                                                                        ON               OFF                                           2nd line potential                                                                           V.sub.2 (≈1.0)                                                                         V.sub.2 (≈1.0)                        ______________________________________                                    

FIG. 14(C) shows a modified example of the semiconductor memory cell ofEmbodiment 6. In the semiconductor memory cell shown in FIG. 14(C), anauxiliary gate (a third conductive gate) G₃ is formed opposite thesecond conductive gate G₂ and facing a third principal surface of thesecond semiconductor channel forming region Ch₂ with a third barrierlayer interposed therebetween. The auxiliary gate G₃ has the function ofshielding the semiconductor forming region Ch₂ from potentials inducedat and ions adhering to the surface of the semiconductor memory cell,thereby ensuring stable operation of the semiconductor memory cell.Furthermore, by connecting the auxiliary gate G₃ to the read/writeselection line, read or write operating margins can be improved. Thesemiconductor memory cell thus constructed has further improvedcharacteristics as compared with the semiconductor memory cell whoseprinciple of operation is shown in FIG. 4.

Embodiment 7

Embodiment 7 is concerned with a semiconductor memory cell according toa fifth aspect of the invention. The semiconductor memory cell ofEmbodiment 7, the principle of operation of which is shown in FIG. 15(A)and a cross section of a portion of which is shown schematically in FIG.15(B), comprises: a first semiconductor region SC₁ of a firstconductivity type (for example, n type); a first conductive region SC₂formed from a material of a second conductivity type opposite to thefirst conductivity type (for example, p⁺) or from other material such asa metal or a silicide that forms a rectifier junction with the firstsemiconductor region SC₁ ; a second semiconductor region SC₃ of thesecond conductivity type (for example, p⁺ type); a second conductiveregion SC₄ formed from a material of the first conductivity type (forexample, n⁺) or from other material such as a metal or a silicide thatforms a rectifier junction with the second semiconductor region SC₃ ;and a conductive gate G disposed in such a manner as to form a bridgeover a barrier layer between the first semiconductor region SC₁ and thesecond conductive region SC₄ and between the first conductive region SC₂and the second semiconductor region SC₃.

The first semiconductor region SC₁ is formed in the surface area of asemiconductor substrate or on an insulating substrate. The firstconductive region SC₂ is formed in the surface area of the firstsemiconductor region SC₁. The second semiconductor region SC₃ is formedin the surface area of the first semiconductor region SC₁ but spacedapart from the first conductive region SC₂. The second conductive regionSC₄ is formed in the surface area of the second semiconductor regionSC₃.

The conductive gate G is connected to a first memory-cell-selection line(for example, a word line). The first conductive region SC₂ is connectedto a write information setting line. The second conductive region SC₄ isconnected to a second memory-cell-selection line (for example, a bitline).

The first semiconductor region SC₁ (corresponding to the channel formingregion Ch₂), the first conductive region SC₂ (corresponding to asource/drain region), the second semiconductor region SC₃ (correspondingto a source/drain region), and the conductive gate G constitute theswitching transistor TR₂. Likewise, the second semiconductor region SC₃(the surface area below the conductive gate G corresponds to the channelforming region Ch₁ (p)), the first semiconductor region SC₁(corresponding to a source/drain region), the second conductive regionSC₄ (corresponding to a source/drain region), and the conductive gate Gconstitute the information storage transistor TR₁.

Potentials applied to the various lines for a memory write aredesignated as follows:

First memory-cell-selection line (e.g., word line): V_(W)

Write information setting line

"0" write: V₀

"1" write: V₁

Read potential is designated as follows:

First memory-cell-selection line (e.g., word line): V_(R)

Also, for a memory read, the potential of the secondmemory-cell-selection line (for example, bit line) to which the secondconductive region SC₄ is connected is designated as follows:

Second memory-cell-selection line: V₂

A fixed potential, including zero potential, is applied to the firstsemiconductor region SC₁.

The threshold voltages of the information storage transistor TR₁required at the conductive gate G for read operations are designated asfollows:

"0" read: V_(TH1).sbsb.--₀

"1" read: V_(TH1).sbsb.--₁

The potential of the channel forming region Ch₁ is different between a"0" read and a "1" read. As a result, the threshold voltage of theinformation storage transistor TR₁ at the conductive gate G differsbetween a "0" read and a "1" read. However, the structure does notrequire the provision of a large capacitor as required in the prior artDRAM.

The potential of the information storage transistor TR₁ is set tosatisfy the following relationship.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

The operation of the semiconductor memory cell of Embodiment 7 will bedescribed below.

Information write

When writing information "0" (write information setting line potential:V₀) or "1" (write information setting line potential: V₁), the potentialof the first line is set at V_(W) (<0). As a result, the potential atthe conductive gate G of the switching transistor TR₂ is also V_(W)(<0). Therefore, the switching transistor TR₂ is ON. Consequently, thepotential of the channel forming region Ch₁ of the information storagetransistor TR₁ is V₀ (when writing information "0") or V₁ (when writinginformation "1". Or V_(W) -V_(TH2) when .linevert split.V_(W) .linevertsplit.<.linevert split.V₁ +V_(TH2) .linevert split.).

During the information retention period after the information is writtenand before the information is read out, the various portions of theinformation storage transistor TR₁ and the switching transistor TR₂ areset at such potentials that neither transistor will conduct. To achievethis, the potential of the first line should be set at 0 (V) and thepotential of the second line at V₁, for example.

When writing information, the potential at the conductive gate G of theinformation storage transistor TR₁ is V_(W) (<0). Therefore, theinformation storage transistor TR₁ is OFF. Thus, when writinginformation "0" or "1", the potential of the channel forming region Ch₁of the information storage transistor TR₁ is V₀ (when writinginformation "0") or V₁ or V_(W) -V_(TH2) (when writing information "1").This condition changes with time because of leakage currents (betweenthe first semiconductor region SC₁ and the semiconductor channel formingregion Ch₁ of the information storage transistor TR₁, off currents ofthe switching transistor TR₂, etc.), but is maintained within anallowable range until the information is read out. The so-call refreshoperation is performed before the change in the potential of the channelforming region Ch₁ of the information storage transistor TR₁ becomeslarge enough to cause errors in read operations.

Information read

When reading information "0" or "1", the potential of the first line isV_(R) (>0). As a result, the potential at the conductive gate G of theswitching transistor TR₂ is V_(R) (>0), and the switching transistor TR₂is OFF.

The potential at the conductive gate G of the information storagetransistor TR₁ is V_(R) (>0). Also, the threshold voltage of theinformation storage transistor TR₁ required at the conductive gate G isV_(TH1).sbsb.--₀ or V_(TH1).sbsb.--₁. The threshold voltage of theinformation storage transistor TR₁ is dependent on the potential of thechannel forming region Ch₁. The following relationship exists betweenthese potentials.

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

Therefore, when the stored information is "0", the information storagetransistor TR₁ is ON. On the other hand, when the stored information is"1", the information storage transistor TR₁ is OFF.

Thus, the information storage transistor TR₁ is set to an ON or OFFcondition, depending on the stored information. Since the secondconductive region SC₄ is connected to the second line, current flows ordoes not flow to the information storage transistor TR₁, depending onthe stored information ("0" or "1"). The stored information can be readout in this manner by the information storage transistor TR₁.

The above-described operating conditions of the information storagetransistor TR₁ and the switching transistor TR₂ are summarized in Table5. The potential values given in Table 5 are only illustrative examples,and each potential can take any value as long as it satisfies the aboveconditions.

                  TABLE 5                                                         ______________________________________                                                     Unit: volts                                                      Memory write   "0" write        "1" write                                     ______________________________________                                        1st line potential                                                                           V.sub.W -3.0     V.sub.W                                                                             -3.0                                    Potential of write                                                                           V.sub.0 0        V.sub.1                                                                             -2.0                                    information setting                                                           line                                                                          Gate potential V.sub.W -3.0     V.sub.W                                                                             -3.0                                    Condition of TR.sub.2                                                                        ON               ON                                            Potential of channel                                                                         V.sub.0 0        V.sub.1                                                                             -2.0                                    forming region                                                                Condition of TR.sub.1                                                                        OFF              OFF                                           ______________________________________                                        Memory read    "0" read         "1" read                                      ______________________________________                                        1st line potential                                                                           V.sub.R 1.0      V.sub.R                                                                             1.0                                     Gate potential V.sub.R 1.0      V.sub.R                                                                             1.0                                     Condition of TR.sub.2                                                                        OFF              OFF                                           Potential of channel                                                                         V.sub.0 0        V.sub.1                                                                             -2.0                                    forming region                                                                Threshold of TR.sub.1                                                                        V.sub.TH1-0                                                                           0.5      V.sub.TH1-1                                                                         1.1                                     required at 1st gate                                                          Condition of TR.sub.1                                                                        ON               OFF                                           2nd line potential                                                                           0.5              0.5                                           ______________________________________                                    

Embodiment 8

Embodiment 8 is concerned with a semiconductor memory cell according toa sixth aspect of the invention. The semiconductor memory cell ofEmbodiment 8, the principle of operation of which is shown in FIG. 16(A)and a cross section of a portion of which is shown schematically in FIG.16(B), comprises: a first semiconductor region SC₁ of a firstconductivity type (for example, n type); a first conductive region SC₂formed from a material of a second conductivity type opposite to thefirst conductivity type (for example, p⁺) or from other material such asa metal or a silicide that forms a rectifier junction with the firstsemiconductor region SC₁); a second semiconductor region SC₃ of thesecond conductivity type (for example, p⁺ type); a second conductiveregion SC₄ formed from a material of the first conductivity type (forexample, n⁺) or from other material such as a metal or a silicide thatforms a rectifier junction with the second semiconductor region SC₃);and a conductive gate G formed in such a manner as to bridge the secondconductive region SC₄ and a portion of the first semiconductor regionSC₁ flanked by the second semiconductor region SC₃ and the firstconductive region SC₂ and also bridge the first conductive region SC₂and the second semiconductor region SC₃. The semiconductor memory cellshown in FIG. 16(B) is depicted in more detail in FIG. 16(C). Forfurther embodiment of the semiconductor memory cell structure shown inFIG. 15(B), part of the structure of the semiconductor memory cellstructure shown in FIG. 16(C) can be applied to the structure shown inFIG. 15(B).

The first semiconductor region SC₁ is formed on a semiconductorsubstrate as an isolated region in the surface area thereof, or on aninsulating substrate as a region attached to a support substrate with aninsulating layer such as an SiO₂ layer interposed therebetween. Thefirst conductive region SC₂ is formed in the surface area of the firstsemiconductor region SC₁. The second semiconductor region SC₃ is formedin the surface area of the first semiconductor region SC₁ but spacedapart from the first conductive region SC₂. The second conductive regionSC₄ is formed in the surface area of the second semiconductor regionSC₃.

The conductive gate G is connected to a first-memory-cell selection line(for example, a word line). The first semiconductor region SC₁ isconnected to a second memory-cell-selection line (for example, a bitline). The first conductive region SC₂ is connected to a first fixedpotential. The second conductive region SC₄ is connected to a secondfixed potential.

The first semiconductor region SC₁ (corresponding to the channel formingregion Ch₂), the first conductive region SC₂ (corresponding to asource/drain region), the second semiconductor region SC₃ (correspondingto a source/drain region), and the conductive gate G constitute theswitching transistor TR₂. Likewise, the second semiconductor region SC₃(the surface area below the conductive gate G corresponds to the channelforming region Ch₁ (p)), the first semiconductor region SC₁(corresponding to a source/drain region), the second conductive regionSC₄ (corresponding to a source/drain region), and the conductive gate Gconstitute the information storage transistor TR₁.

The first fixed potential to which the first conductive region SC₂ isconnected is designated as V₃ (≦0). Likewise, the second fixed potentialto which the second conductive region SC₄ is connected is designated asV₄ (≧0).

Potentials applied to the various lines for a memory write aredesignated as follows:

First memory-cell-selection line (e.g., word line): V_(W)

Second memory-cell-selection line (e.g., bit line)

"0" write: V₀

"1" write: V₁

Likewise, the threshold voltages of the switching transistor TR₂required at the conductive gate for write operations are designated asfollows:

"0" write: V_(TH2W).sbsb.--₀

"1" write: V_(TH2W).sbsb.--₁

Read potential is designated as follows:

First memory-cell-selection line (e.g., word line): V_(R)

Also, the threshold voltages of the information storage transistor TR₁required at the conductive gate G for read operations are designated asfollows:

"0" read: V_(TH1R).sbsb.--₀

"1" read: V_(TH1E).sbsb.--₁

Generally, the potentials of the channel forming regions Ch₁ and Ch₂ aredifferent between a "0" read/write and a "1" read/write. As a result,the threshold voltages of the information storage transistor TR₁ and theswitching transistor TR₂ required at the conductive gate G differbetween a "0" read/write and a "1" read/write. However, the structuredoes not require the provision of a large capacitor as required in theprior art DRAM. The potential at the conductive gate of the switchingtransistor TR₂, relative to V_(W), is set as shown below, for example,for simplicity of explanation.

    .linevert split.V.sub.W .linevert split.>.linevert split.V.sub.TH2W.sbsb.--.sub.1 .linevert split. or .linevert split.V.sub.TH2W.sbsb.--.sub.0 .linevert split. whichever larger

The potential at the conductive gate of the information storagetransistor TR₁, relative to V_(R), is set as follows:

    .linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.

The operation of the semiconductor memory cell of Embodiment 8 will bedescribed below.

Information write

When writing information "0" (second line potential: V₀) or "1" (secondline potential: V₁), the potential of the first line is set at V_(W)(<0). As a result, the potential at the conductive gate G of theswitching transistor TR₂ is also V_(W) (<0). V_(W) is

    .linevert split.V.sub.W .linevert split.>.linevert split.V.sub.TH2W.sbsb.--.sub.1 .linevert split. or .linevert split.V.sub.TH2W.sbsb.--.sub.0 .linevert split. whichever larger

Therefore, for a write operation, the switching transistor TR₂ is ON.Consequently, the potential of the channel forming region Ch₁ of theinformation storage transistor TR₁ is

"0" information write: V₃

"1" information write: V₃

When writing information, the potential at the conductive gate G of theinformation storage transistor TR₁ is V_(W) (<0). Therefore, theinformation storage transistor TR₁ is OFF. Thus, when writinginformation "0" or "1", the potential of the channel forming region Ch₁of the information storage transistor TR₁ is V₃ for both "0" and "1"information write. During the retention period, since TR₂ is also OFF,when the second line potential at this time is denoted by V₅ (.linevertsplit.V₅ .linevert split.≦.linevert split.V₀ .linevert split. or.linevert split.V₁ .linevert split.) the potential of the firstsemiconductor channel Ch₁ is γ{V₃ -(V₀ -V₅)} or γ{V₃ -(V₁ -V₅)}, where γis the ratio of the capacitance between the first semiconductor regionSC₁ and the second semiconductor region SC₃ to the total capacitancebetween the second semiconductor region SC₃ and the other areas(including the first semiconductor region SC₁) than the secondsemiconductor region SC₃. This condition changes with time because ofleakage currents (between the first semiconductor region SC₁ and thesemiconductor channel forming region Ch₁ of the information storagetransistor TR₁, off currents of the switching transistor TR₂, etc.), butis maintained within an allowable range until the information is readout.

During the information retention period after the information is writtenand before the information is read out, the various portions of theinformation storage transistor TR₁ and the switching transistor TR₂ areset at such potentials that neither transistor will conduct. To achievethis the potential of the first line should be set at 0 (V) and thepotential of the second line at V₅, for example. The so-called refreshoperation is performed before the change in the potential of the channelforming region Ch₁ of the information storage transistor TR₁ becomeslarge enough to cause errors in read operations.

Information read

When reading information "0" or "1", the potential of the first line isV_(R) (>0), and the potential of the second line is V₆ (.linevertsplit.V₆ .linevert split.≦.linevert split.V₀ .linevert split. or.linevert split.V₁ .linevert split.). As a result, the potential at theconductive gate G of the switching transistor TR₂ is V_(R) (>0), and theswitching transistor TR₂ is OFF.

The potential at the conductive gate G of the information storagetransistor TR₁ is V_(R) (>0). Also, the threshold voltage of theinformation storage transistor TR₁ required at the first conductive gateG₁ is V_(TH1R).sbsb.--₀ or V_(TH1R).sbsb.--₁ which is given by thepotential between the second semiconductor region SC₃ and the secondconductive region SC₄ when γ{V₃ -(V₀ -V₆)} or γ{V₃ -(V₁ -V₆)} is met.The threshold voltage of the information storage transistor TR₁ isdependent on the potential of the channel forming region Ch₁. Thefollowing relationship exists between these potentials.

    .linevert split.V.sub.TH1.sbsb.--.sub.0 .linevert split.>.linevert split.V.sub.R .linevert split.>.linevert split.V.sub.TH1.sbsb.--.sub.1 .linevert split.

Therefore, when the stored information is "0", the information storagetransistor TR₁ is OFF. On the other hand, when the stored information is"1", the information storage transistor TR₁ is ON.

Thus, the information storage transistor TR₁ is set to an ON or OFFcondition, depending on the stored information. Since the secondconductive region SC₄ is connected to the second fixed potential,current flows or does not flow to the information storage transistorTR₁, depending on the stored information ("0" or "1"). The storedinformation can be read out in this manner by the information storagetransistor TR₁.

The above-described operating conditions of the information storagetransistor TR₁ and the switching transistor TR₂ are summarized in Table6. The potential values given in Table 6 are only illustrative examples,and each potential can take any value as long as it satisfies the aboveconditions.

                  TABLE 6                                                         ______________________________________                                                  Unit: volts                                                         Memory write                                                                              "0" write      "1" write                                          ______________________________________                                        1st line potential                                                                        V.sub.W  -2.0      V.sub.W                                                                              -2.0                                    2nd line potential                                                                        V.sub.0  2.0       V.sub.1                                                                              0                                       1st fixed potential  V.sub.2          V.sub.2                                 Gate potential                                                                            V.sub.W  -2.0      V.sub.W                                                                              -2.0                                    Thereshold of TR.sub.2                                                                    V.sub.TH2W-0                                                                           -1.2      V.sub.TH2W-1                                                                         -0.5                                    required at gate                                                              Condition of TR.sub.2                                                                     ON             ON                                                 Potential of TR.sub.1                                                                              1st fixed        1st fixed                               channel forming      potential        potential                               region               e.g. 0           e.g. 0                                  Condition of TR.sub.1                                                                     OFF            OFF                                                ______________________________________                                        Memory read "0" read       "1" read                                           ______________________________________                                        1st line potential                                                                        V.sub.R  1.0       V.sub.R                                                                              1.0                                     Gate potential                                                                            V.sub.R  1.0       V.sub.R                                                                              1.0                                     Condition of TR.sub.2                                                                     OFF            OFF                                                Potential of TR.sub.1                                                                              -0.75            +0.25                                   channel forming                                                               region                                                                        Threshold of TR.sub.1                                                                     V.sub.TH1R-0                                                                           0.85      V.sub.TH1R-1                                                                         0.5                                     required at 1st gate                                                          Condition of TR.sub.1                                                                     OFF            ON                                                 2nd line potential                                                                        0.5            0.5                                                2nd fixed potential                                                                       0.25           0.25                                               ______________________________________                                    

The semiconductor memory cell of the invention has been described abovein accordance with preferred embodiments, but it will be appreciatedthat the invention is not limited to those described preferredembodiments. For example, in the first and second aspects of theinvention described in Embodiments 1 and 3, the information storagetransistor TR₁ and the switching transistor TR₁ may be both formed fromp-type transistors. Furthermore, in the preferred modes of the first andsecond aspects of the invention described in Embodiments 2 and 4, theinformation storage transistor TR₁ may be formed from an n-typetransistor and the switching transistor TR₂ from a p-type transistor.Moreover, in the third to fifth aspects described in Embodiments 5 to 8,the information storage transistor TR₁ may be formed from a p-typetransistor and the switching transistor TR₂ from an n-type transistor.It will also be appreciated that the arrangement of elements in eachtransistor shown is only illustrative and may be modified as needed.

The present invention is applicable not only to memory cells formed fromsilicon semiconductors but also to memory cells formed from compoundsemiconductors such as GaAs, for example.

In the semiconductor memory cell of the present invention, the operationof the information storage transistor is determined in dependingrelationship on the potential or charge (information) stored on thesecond conductive gate or in the channel forming region of theinformation storage transistor, and the information read out as thetransistor current during refresh intervals is independent of themagnitude of the capacitance of a capacitor (for example, thecapacitance of the second conductive gate plus added capacitance, etc.)if such a capacitor is added. This therefore serves to solve the problemof capacitor capacitance encountered in prior art semiconductor memorycells; if a capacitor is added for refresh interval adjustment, a verylarge capacitor such as those required in the prior art DRAMs is notrequired. Furthermore, the maximum area of the semiconductor memory cellis equal to or smaller than the area of two transistors.

In the semiconductor memory cell according to the first and secondaspects of the invention, a conductive gate is provided opposite each oftwo principal surfaces of the semiconductor channel layer of theinformation storage transistor. This structure eliminates the problem ofunstable transistor operation inherent in prior art transistorstructures; that is, the structure of the invention is effective instabilizing the operation of the information storage transistor, andfacilitates short-channel transistor design. The first conductive gateand the third conductive gate are both connected to the firstmemory-cell-selection line. Accordingly, the first memory-cell-selectionline need not be provided more than one, and the chip area can bereduced. Furthermore, depending on the structure, it is possible to forma memory cell within an area equal to one transistor area.

In the semiconductor memory cell according to the second aspect of theinvention, a fourth gate is provided as an extra gate of the switchingtransistor. The provision of this extra gate serves to further stabilizethe operation of the switching transistor.

In the preferred modes of the semiconductor memory cell according to thefirst and second aspects of the invention, a fifth conductive layer isprovided. The provision of this fifth conductive layer prevents withoutfail a current from flowing to the information storage transistor duringthe information write operation.

The semiconductor memory cell fabrication process according to the thirdaspect of the invention is compatible with the fabrication process forCMOS ASICs, as shown, for example, in FIG. 12(B). The process thereforeallows DRAM functions to be incorporated in an ASIC without requiringextra processing steps although the semiconductor memory cell areaincreases slightly. On the other hand, in the semiconductor memory cellstructure shown in FIG. 12(C), for example, one extra processing stepmay be required as compared to the CMOS ASIC structure, but thesemiconductor memory cell area can be reduced nearly by half.

According to the fourth aspect of the invention, the semiconductormemory cell can be implemented on an area approximately equal to onetransistor area.

According to the fifth and sixth aspects of the invention, thesemiconductor memory cell can be implemented on an area approximatelyequal to one transistor area by using conventional semiconductor memorycell fabrication techniques without relying on SOI technology.

What is claimed is:
 1. A semiconductor memory cell comprising:a firstsemiconductor region of a first conductivity type formed in a surfaceregion of a semiconductor substrate or on an insulating substrate, afirst conductive region formed in a surface region of said firstsemiconductor region in contacting relationship forming a rectifierjunction therebetween, a second semiconductor region of a secondconductivity type formed in a surface region of said first semiconductorregion but spaced apart from said first conductive region, a secondconductive region formed in a surface region of said secondsemiconductor region in contacting relationship forming a rectifierjunction therebetween, and a conductive gate disposed in such a manneras to form a bridge over a barrier layer between said firstsemiconductor region and said second conductive region and between saidfirst conductive region and said second conductive region, whereinsaidconductive gate is connected to a first memory-cell-selection line, andsaid first semiconductor region is connected to a secondmemory-cell-selection line.